Email: Apple eyes NVLink 🔗, Crusoe targets modular datacenters 🏗️, How Apple silicon got faster ⚡

Subject:
Apple eyes NVLink 🔗, Crusoe targets modular datacenters 🏗️, How Apple silicon got faster ⚡
Received:
9/21/2026, 1:11:53 PM
From:
"TLDR Hardware" <dan@tldrnewsletter.com>
To:
silk.theater.56@fwdnl.com
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&lt;div style="display: none; max-height: 0px; overflow: hidden;"&gt;Apple is developing AI servers built around its own M8 Ultra chips, in two- and four-chip configurations, and evaluating Nvidia&#039;s NVLink Fusion&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;‌&nbsp;&lt;/div&gt;

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&lt;h1&gt;&lt;strong&gt;TLDR Hardware &lt;span id="date"&gt;2026-09-21&lt;/span&gt;&lt;/strong&gt;&lt;/h1&gt;
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&lt;div style="text-align: center;"&gt;&lt;span style="font-size: 36px;"&gt;📱&lt;/span&gt;&lt;/div&gt;&lt;/div&gt;
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&lt;h1&gt;&lt;strong&gt;Headlines and Launches&lt;/strong&gt;&lt;/h1&gt;
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                                &lt;a href="https://tracking.tldrnewsletter.com/CL0/https:%2F%2Fwww.tomshardware.com%2Ftech-industry%2Fartificial-intelligence%2Fapple-eyes-nvidia-nvlink-to-power-its-new-custom-m8-ultra-ai-servers-historically-bitter-rivals-reportedly-team-up-for-2029-data-center-push%3Futm_source=tldrhardware/1/010001a0c4182b59-784d442a-7258-485d-ab99-b967915672d8-000000/MseYoGR_Zb5TvdM3mJf0nko684OX4Ipn7HipYqItJwc=452"&gt;
                                    &lt;span&gt;
                                        &lt;strong&gt;Apple reportedly eyes Nvidia's NVLink Fusion to connect its own M8 Ultra AI servers by 2029 (5 minute read)&lt;/strong&gt;
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&lt;br&gt;
&lt;span style="font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, Verdana, sans-serif;"&gt;
                                    Apple is developing AI servers built around its own M8 Ultra chips, in two- and four-chip configurations, and evaluating Nvidia's NVLink Fusion, the interconnect protocol, switches, chiplets, and software stack Nvidia uses to bind racks of GPUs into one tightly coupled compute domain, since Apple's own UltraFusion tech stitches two chips together but has no answer for the larger-scale connectivity these servers would need.
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                                &lt;a href="https://tracking.tldrnewsletter.com/CL0/https:%2F%2Ftechcrunch.com%2F2026%2F09%2F17%2Fcrusoe-raises-3-9b-to-build-massive-data-centers-and-small-modular-ai-factories%2F%3Futm_source=tldrhardware/1/010001a0c4182b59-784d442a-7258-485d-ab99-b967915672d8-000000/fcRNQ6XPCmzkLgvzdgO1PrUySwfSMRHqMc_1jXculwU=452"&gt;
                                    &lt;span&gt;
                                        &lt;strong&gt;Crusoe raises $3.9B to build massive data centers and truck-transportable modular "Spark" AI factories (3 minute read)&lt;/strong&gt;
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&lt;br&gt;
&lt;span style="font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, Verdana, sans-serif;"&gt;
                                    Crusoe raised a $3.9 billion Series F, pushing its valuation to $30.9 billion, with the capital funding both large-scale sites like its Abilene, Texas data center used by OpenAI, and Spark, a line of smaller modular data centers Crusoe manufactures at its own facilities so they can be transported by truck and connected to power almost anywhere. Building these in-house lets Crusoe deploy compute fast without needing a large on-site construction workforce, and the smaller footprint helps sidestep some of the local community backlash that larger data center complexes increasingly draw.
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&lt;div style="text-align: center;"&gt;&lt;span style="font-size: 36px;"&gt;🔨&lt;/span&gt;&lt;/div&gt;
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&lt;h1&gt;&lt;strong&gt;Engineering and Applications&lt;/strong&gt;&lt;/h1&gt;
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&lt;span&gt;
                                &lt;a href="https://tracking.tldrnewsletter.com/CL0/https:%2F%2Finterestingengineering.com%2Finnovation%2Fchina-older-chipmaking-technology-smaller-chips%3Futm_source=tldrhardware/1/010001a0c4182b59-784d442a-7258-485d-ab99-b967915672d8-000000/U-wVDrFdiPmhFsI1sTIwUoabROpQXgr-PZW-Ok9sHVo=452"&gt;
                                    &lt;span&gt;
                                        &lt;strong&gt;China builds early sub-3nm GAA transistors using older DUV lithography, sidestepping EUV restrictions (4 minute read)&lt;/strong&gt;
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&lt;span style="font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, Verdana, sans-serif;"&gt;
                                    Chinese Academy of Sciences researchers have completed early integration of stacked nanosheet-channel gate-all-around (GAA) CMOS transistors, the architecture already used by Samsung and TSMC at 3nm and below, using deep ultraviolet (DUV) lithography instead of the EUV machines ASML is barred from selling to China. GAA wraps the gate fully around the channel rather than surrounding it on three sides like FinFET, giving tighter control over current flow. Researcher Ye Tianchun frames the work as an early process route toward sub-3nm devices rather than a demonstrated production capability.
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&lt;div style="text-align: center;"&gt;&lt;span style="font-size: 36px;"&gt;🧠&lt;/span&gt;&lt;/div&gt;
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&lt;h1&gt;&lt;strong&gt;Research and Prototypes&lt;/strong&gt;&lt;/h1&gt;
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&lt;div class="text-block"&gt;
&lt;span&gt;
                                &lt;a href="https://tracking.tldrnewsletter.com/CL0/https:%2F%2Ftech.yahoo.com%2Fscience%2Farticles%2Fmaterial-conducts-5-times-less-175712237.html%3Futm_source=tldrhardware/1/010001a0c4182b59-784d442a-7258-485d-ab99-b967915672d8-000000/LCtYdGvijUtb-Qkh8Ogh0R1f7cZk1OILzwSRb5okyac=452"&gt;
                                    &lt;span&gt;
                                        &lt;strong&gt;NC State's new thin film is 10,000x stiffer than silicone, yet insulates 5x better (4 minute read)&lt;/strong&gt;
                                    &lt;/span&gt;
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&lt;br&gt;
&lt;span style="font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, Verdana, sans-serif;"&gt;
                                    Material science has long treated stiffness and heat insulation as a trade-off: stiff materials like metal conduct heat fast, while soft ones like rubber trap it. NC State researchers broke that link with a non-porous thin film built from 2D hybrid organic-inorganic perovskites, arranging alternating organic and inorganic layers into precise crystalline structures and swapping standard carbon chains for custom-tailored benzene rings to trap heat vibrations without sacrificing structural rigidity.
                                &lt;/span&gt;
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&lt;span&gt;
                                &lt;a href="https://tracking.tldrnewsletter.com/CL0/https:%2F%2Fnewsroom.ucla.edu%2Freleases%2Ftoward-physical-ai-when-hardware-becomes-neural-network%3Futm_source=tldrhardware/1/010001a0c4182b59-784d442a-7258-485d-ab99-b967915672d8-000000/I89yX_MKT8762xGfgtfGF-RRVDI7BKfrqtSq2fMaIms=452"&gt;
                                    &lt;span&gt;
                                        &lt;strong&gt;UCLA-pioneered nanowire networks physically rewire themselves to compute, no software neural network required (4 minute read)&lt;/strong&gt;
                                    &lt;/span&gt;
&lt;/a&gt;
&lt;br&gt;
&lt;br&gt;
&lt;span style="font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, Verdana, sans-serif;"&gt;
                                    A new paper in Nature Reviews Physics covers self-organizing nanowire and nanoparticle networks, first built at UCLA in 2011, where the material's physical structure acts as the neural network instead of running one in software on a chip. Individual nanowires act like neurons, and the connections between them act like synapses, growing stronger with repeated use and fading without it, similar to memory and forgetting in the brain, so the hardware itself learns rather than just running a fixed program.
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&lt;div style="text-align: center;"&gt;&lt;span style="font-size: 36px;"&gt;🎁&lt;/span&gt;&lt;/div&gt;&lt;/div&gt;
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&lt;div style="text-align: center;"&gt;&lt;strong&gt;&lt;h1&gt;Miscellaneous&lt;/h1&gt;&lt;/strong&gt;&lt;/div&gt;
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&lt;table align="center" border="0" cellpadding="0" cellspacing="0" width="100%"&gt;&lt;tbody&gt;&lt;tr&gt;&lt;td class="container" style="padding: 15px 15px;"&gt;
&lt;div class="text-block"&gt;
&lt;span&gt;
                                &lt;a href="https://tracking.tldrnewsletter.com/CL0/https:%2F%2Flemire.me%2Fblog%2F2026%2F09%2F19%2Fhow-did-apple-silicon-get-50-faster-in-three-years%2F%3Futm_source=tldrhardware/1/010001a0c4182b59-784d442a-7258-485d-ab99-b967915672d8-000000/tcxg9n4t5riihXTNnFIRAy7VBeeC7w6KcrjoJGje6-w=452"&gt;
                                    &lt;span&gt;
                                        &lt;strong&gt;Daniel Lemire breaks down how Apple Silicon got 52% faster in three years, mostly from clock speed (4 minute read)&lt;/strong&gt;
                                    &lt;/span&gt;
&lt;/a&gt;
&lt;br&gt;
&lt;br&gt;
&lt;span style="font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, Verdana, sans-serif;"&gt;
                                    Comparing base M2 (2022) through M5 (2025) on Geekbench 6, single-core performance rose 52% and multi-core 83%, with most of the single-core gain traced to raw clock speed: the P-core climbed from 3.5GHz to 4.6GHz, a 30% jump that alone explains the bulk of it. Transistor count grew roughly 40% from M2 to M4 (20 billion to 28 billion), spent partly on two extra efficiency cores on the M4 that boost multicore throughput without touching single-core speed, and partly on wider decode, up from 8 to 10 instructions per cycle, ahead of most competitors.
                                &lt;/span&gt;
&lt;/span&gt;
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&lt;table align="center" border="0" cellpadding="0" cellspacing="0" width="100%"&gt;&lt;tbody&gt;&lt;tr&gt;&lt;td class="container" style="padding: 15px 15px;"&gt;
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&lt;span&gt;
                                &lt;a href="https://tracking.tldrnewsletter.com/CL0/https:%2F%2Flinks.tldrnewsletter.com%2FlWtDmY/1/010001a0c4182b59-784d442a-7258-485d-ab99-b967915672d8-000000/u_zEbSPWxygGKCOE9k5f5MAx2_iAxA5xrYHh0X4SnUI=452"&gt;
                                    &lt;span&gt;
                                        &lt;strong&gt;Cerebras CEO Andrew Feldman on the "dinner plate" chip, and why AI inference today is "utterly idiotic" (6 minute read)&lt;/strong&gt;
                                    &lt;/span&gt;
&lt;/a&gt;
&lt;br&gt;
&lt;br&gt;
&lt;span style="font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, Verdana, sans-serif;"&gt;
                                    At a Google Bay View event, Cerebras co-founder Andrew Feldman, semiconductor veteran Atiq Raza, and investor Dave Blundin discussed where AI hardware is actually bottlenecked. Feldman brought Cerebras's WSE-3 "dinner plate" chip, a 9-inch wafer-scale part with 4 trillion transistors across 900,000 cores, now carrying a $25 billion backlog with plans to scale production 8x this year and again next year, and named data center availability, not compute itself, as the industry's current binding constraint, predicting fab capacity becomes the next bottleneck within three years.
                                &lt;/span&gt;
&lt;/span&gt;
&lt;/div&gt;
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&lt;div class="text-block"&gt;
&lt;div style="text-align: center;"&gt;&lt;span style="font-size: 36px;"&gt;⚡&lt;/span&gt;&lt;/div&gt;&lt;/div&gt;
&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;

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&lt;div style="text-align: center;"&gt;

&lt;h1&gt;&lt;strong&gt;Quick Links&lt;/strong&gt;&lt;/h1&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;

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&lt;div class="text-block"&gt;
&lt;span&gt;
                                &lt;a href="https://tracking.tldrnewsletter.com/CL0/https:%2F%2Finterestingengineering.com%2Fspace%2Fus-ghost-r-spy-satellite-prototyp%3Futm_source=tldrhardware/1/010001a0c4182b59-784d442a-7258-485d-ab99-b967915672d8-000000/PrOIZ48u4hTabLhkO9Pt7zpL7oaMyENzWHqBOhv8A8A=452"&gt;
                                    &lt;span&gt;
                                        &lt;strong&gt;Northrop Grumman Wins GHOST-R Spy Satellite Prototype Deal (3 minute read)&lt;/strong&gt;
                                    &lt;/span&gt;
&lt;/a&gt;
&lt;br&gt;
&lt;br&gt;
&lt;span style="font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, Verdana, sans-serif;"&gt;
                                    Northrop Grumman won a Space Force/DIU contract to build a GHOST-R prototype satellite, using its compact suitcase-sized ESPASat-L platform with a TRL-11 optical payload, to deliver low-cost, high-resolution surveillance of objects in geosynchronous orbit within an accelerated 24-month timeline.
                                &lt;/span&gt;
&lt;/span&gt;
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&lt;div class="text-block"&gt;
&lt;span&gt;
                                &lt;a href="https://tracking.tldrnewsletter.com/CL0/https:%2F%2Ftechcrunch.com%2F2026%2F09%2F18%2Fjoby-aviations-3100-mile-autonomous-flight-signals-its-push-beyond-electric-air-taxis%2F%3Futm_source=tldrhardware/1/010001a0c4182b59-784d442a-7258-485d-ab99-b967915672d8-000000/rarYkz_v_zGcpY5xXuCUWlkjBNL09qu3-SCCSra9wlU=452"&gt;
                                    &lt;span&gt;
                                        &lt;strong&gt;Joby's autonomy stack flies a converted Cessna 3,100 miles across the US, no pilot in control (3 minute read)&lt;/strong&gt;
                                    &lt;/span&gt;
&lt;/a&gt;
&lt;br&gt;
&lt;br&gt;
&lt;span style="font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, Verdana, sans-serif;"&gt;
                                    Joby Aviation flew a converted Cessna Caravan more than 3,100 miles across the US with autonomous taxiing, takeoff, navigation, and landing throughout, remotely supervised from Joby's California headquarters and Shaw Air Force Base, with a pilot onboard only for compliance.
                                &lt;/span&gt;
&lt;/span&gt;
&lt;/div&gt;
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&lt;div class="text-block"&gt;
&lt;span&gt;
                                &lt;a href="https://tracking.tldrnewsletter.com/CL0/https:%2F%2Fwww.eetimes.com%2Fu-s-awards-anderon-1b-for-quantum-wafer-manufacturing%3Futm_source=tldrhardware/1/010001a0c4182b59-784d442a-7258-485d-ab99-b967915672d8-000000/UfBtMGr2ErM0ZrsWYdG5NWSa6ERJsYbQZo0s_E2SMmE=452"&gt;
                                    &lt;span&gt;
                                        &lt;strong&gt;US awards Anderon $1B to build dedicated quantum wafer manufacturing (3 minute read)&lt;/strong&gt;
                                    &lt;/span&gt;
&lt;/a&gt;
&lt;br&gt;
&lt;br&gt;
&lt;span style="font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, Verdana, sans-serif;"&gt;
                                    Anderon, IBM's Albany-based quantum chip foundry spinout, secured a $1 billion CHIPS Act award to scale up US production of 300mm quantum wafers.
                                &lt;/span&gt;
&lt;/span&gt;
&lt;/div&gt;
&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;

&lt;table align="center" border="0" cellpadding="0" cellspacing="0" width="100%"&gt;&lt;tbody&gt;&lt;tr&gt;&lt;td class="container" style="padding: 15px 15px;"&gt;
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&lt;span&gt;
                                &lt;a href="https://tracking.tldrnewsletter.com/CL0/https:%2F%2Fwww.thelec.net%2Fnews%2FarticleView.html%3Fidxno=14007%26utm_source=tldrhardware/1/010001a0c4182b59-784d442a-7258-485d-ab99-b967915672d8-000000/kAVW0JIe_vF4ahSUA9B6xCtb7aTZgqLjtjDxGORBy-w=452"&gt;
                                    &lt;span&gt;
                                        &lt;strong&gt;Lattice launches Mach-N2, an FPGA built for the post-quantum security era (4 minute read)&lt;/strong&gt;
                                    &lt;/span&gt;
&lt;/a&gt;
&lt;br&gt;
&lt;br&gt;
&lt;span style="font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, Verdana, sans-serif;"&gt;
                                    Lattice Semiconductor unveiled Mach-N2, an FPGA that beats rivals AMD Xilinx and Altera to market with post-quantum cryptography (PQC) baked in.
                                &lt;/span&gt;
&lt;/span&gt;
&lt;/div&gt;
&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;

&lt;table align="center" border="0" cellpadding="0" cellspacing="0" width="100%"&gt;&lt;tbody&gt;&lt;tr&gt;&lt;td class="container" style="padding: 15px 15px;"&gt;
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&lt;span&gt;
                                &lt;a href="https://tracking.tldrnewsletter.com/CL0/https:%2F%2Fthenextweb.com%2Fnews%2Fnexperia-tata-electronics-chip-manufacturing-india%3Futm_source=tldrhardware/1/010001a0c4182b59-784d442a-7258-485d-ab99-b967915672d8-000000/g6M-ylonp_FnC6YOE8Bi2KNBchzIakeFBhgD2BN14GU=452"&gt;
                                    &lt;span&gt;
                                        &lt;strong&gt;Nexperia will make chips in India with Tata as it splits from Wingtech (3 minute read)&lt;/strong&gt;
                                    &lt;/span&gt;
&lt;/a&gt;
&lt;br&gt;
&lt;br&gt;
&lt;span style="font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, Verdana, sans-serif;"&gt;
                                    Nexperia will have Tata make and package chips in India, expanding its manufacturing options as it separates from Chinese parent Wingtech.
                                &lt;/span&gt;
&lt;/span&gt;
&lt;/div&gt;
&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;

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